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micrf6 10 868-870mhz ism band transceiver module radiowire? is a trademark of mic r el, inc. micrel inc. ? 2180 fortu ne drive ? san jose, ca 95131 ? usa ? tel +1 ( 40 8 ) 944 -08 00 ? fax + 1 (408) 474-1000 ? htt p :/ /www.micrel.com july 200 6 m999 9-12 020 5 general description the mi crf6 10 i s a self-containe d fre q uen cy shift keying (fsk) tra n sceiver mo dule, intende d for use i n half-d uplex, bidire ction a l rf links. the mu lti-cha nnel ed fsk transceive r m odule is inten ded fo r uhf radio eq uipm ent in compli an ce with eu rop e a n tel e comm unication sta ndard institute (etsi) spe c ificatio n en300 2 20. the tran smit ter con s ist s of a fully p r ogra mmabl e pll freque ncy synthesi z e r an d power a m plif ier. the f r equ ency synthe sizer con s i s ts of a voltage-co ntrolled oscil l ator (vco ), a crystal o scill a t or, dual m odulu s p r e s cale r, prog ram m abl e freq uen cy divider s, an d a ph ase-d e tector. the output po wer of the p o wer amplifie r can b e prog ram m ed to seve n leve ls. a lo ck-d etect circuit det ects when the pll is in lock. in receive m ode, the pll synthesi z e r gene rate s the local oscillator (lo) signal. the n, m, and a values that gi ve the lo freq uen cy are sto r ed in the n0, m0, a nd a0 regi ste r s. the receiver i s a ze ro inte rm ediate frequ ency (if) type that make s cha n n e l f ilt ering po ssi b le w i th low - po we r , in teg r a t ed low-pass filters. the receiv er con s i s ts of a lo w noise amplifier (l na) that drive s a qu adrat ure mix pai r. the mixer output s feed two ide n tical si gnal cha nnel s in p hase quad ratu re. each ch anne l inclu d e s a p r e-amplifie r, a third o r d e r sa llen- ke y rc low - pa ss filter that prote c ts the followin g swi t ched -capa cit o r filter fro m stro ng a d j ace n t cha nnel sig n a ls, an d a lim iter. the m a i n ch ann el filter i s a swit ched-capacitor implementation of a six-pol e ellipti c low pass filter. th e cut - off freq uen cy of the sallen-key rc filter can be prog rammed to fo ur different f r eque nci e s: 1 00khz, 150 khz, 230 khz, an d 3 50khz. the i and q chann el outputs are demo dulate d an d p r od uce a digita l data output. the d e modul ator d e tects th e rel a tive pha se o f the i and the q chann el si gna l. if the i channel sig nal lag s behin d the q ch ann el, the fsk tone freque ncy i s a bove the lo frequ ency (d ata ?1 ?). if the i channel lea d s t he q cha nnel, the n the fsk tone i s bel ow the lo freq uen cy (data ?0 ?). t he o u tput of the receiver is avail able o n the dataixo pin. a receive signal strengt h indicato r (rssi) circuit i ndi ca tes the rece ived si gnal l e vel. all su pport documentatio n can be fo und on micrel?s we b site at: ww w. mic r el. c om. ra diowir e ? module fe ature s ? ?d rop in ? rf solutio n ? small size: 11.5x14.1mm ? r f tes t ed ? low po we r ? surface mou n table ? tape & re el ? digital bit synch r o n izer ? re ceived sig nal strength i ndicator (rs s i) ? rx and tx p o we r man age ment ? powe r do wn functio n ? regi ste r rea d back functio n applicati o ns ? telemet r y ? r e mote metering ? wireless cont roller ? rem o te data rep eater ? rem o t e co nt r o l sy st em s ? wir e le ss mo d e m ? wir e le ss se c u rit y sy st em
micrel, inc. MICRF610/MICRF610z july 2006 2 m9999-120205 contents general description ................................................................................................................................................................ 1 features .................................................................................................................................................................................. 1 applications ............................................................................................................................................................................. 1 contents .................................................................................................................................................................................. 2 radiowire ? rf module selection guide ................................................................................................................................. 3 ordering information ............................................................................................................................................................... 3 block diagram ......................................................................................................................................................................... 3 pin configuration ..................................................................................................................................................................... 4 pin description ........................................................................................................................................................................ 4 absolute maximum ratings (1) ................................................................................................................................................. 5 operating ratings (2) ................................................................................................................................................................ 5 electrical characteristics ......................................................................................................................................................... 5 programming ........................................................................................................................................................................... 7 general ............................................................................................................................................................................... 7 writing to the control registers in MICRF610 ................................................................................................................... 8 writing to a single register ................................................................................................................................................ 8 writing to all registers ....................................................................................................................................................... 8 writing to n registers having incremental addresses ....................................................................................................... 9 reading from the control registers in MICRF610 ............................................................................................................. 9 reading n registers from MICRF610 ................................................................................................................................. 9 programming interface timing ............................................................................................................................... ............... 10 power on reset ............................................................................................................................... ................................. 11 programming summary ............................................................................................................................... ..................... 11 frequency synthesizer ............................................................................................................................... .......................... 12 crystal oscillator (xco) ............................................................................................................................... .................... 12 vco ............................................................................................................................... ................................................... 12 lock detect ............................................................................................................................... ........................................ 13 modes of operation ............................................................................................................................... ................................ 13 transceiver sync/non-synchronous mode ...................................................................................................................... 14 data interface ............................................................................................................................... .................................... 14 receiver ............................................................................................................................... ................................................. 14 front end ............................................................................................................................... ........................................... 15 sallen-key filters ............................................................................................................................... ............................... 15 switched capacitor filter ............................................................................................................................... ................... 15 rssi ............................................................................................................................... ................................................... 15 fee ............................................................................................................................... .................................................... 16 bit synchronizer ............................................................................................................................... ................................. 16 transmitter ............................................................................................................................... ............................................. 17 power amplifier ............................................................................................................................... .................................. 17 frequency modulation ............................................................................................................................... ....................... 17 using the xco-tune bits ............................................................................................................................... ........................ 17 application circuit illustration ............................................................................................................................... ................. 18 assembling the MICRF610 ............................................................................................................................... .................... 18 recommended reflow temperature profile .................................................................................................................... 18 shock/vibration during reflow ............................................................................................................................... ........... 18 handassembling the MICRF610 ............................................................................................................................... ........ 18 layout ............................................................................................................................... ..................................................... 19 recommended land pattern ............................................................................................................................... ............. 19 layout considerations ............................................................................................................................... ....................... 19 package dimensions ............................................................................................................................... ............................. 20 tape dimensions ............................................................................................................................... ................................... 20
mic r el, inc . micrf 610/m i crf 610z july 200 6 3 m999 9-12 020 5 radiowire ? rf modul e sel ection gui d e de v i c e fr e que ncy r a n g e d a t a r a t e rec e i v e supply vo ltag e t ran s m i t modu la tion t y p e p a c k ag e micrf 600 902- 928 mhz < 20 kbps 13.5 ma 2.0-2.5 v 28 ma f sk 11.5 x 1 4 .1 mm micrf 600z l e a d - f r e e mic r f 6 0 0 micrf 610 868- 870 mhz < 15 kbps 13.5 ma 2.0-2.5 v 28 ma f sk 11.5 x 1 4 .1 mm micrf 610z l e a d - f r e e mic r f 6 1 0 micrf 620 430- 440 mhz < 20 kbps 12.0 ma 2.0-2.5 v 24 ma f sk 11.5 x 1 4 .1 mm micrf 620z l e a d - f r e e mic r f 6 2 0 rf b433b 430- 440 mhz 19.2 kba ud 8 ma 2.5-3.4 v 42 ma f sk 1?x1? rf b868b 868- 870 mhz 19.2 kba ud 10 ma 2.5-3.4 v 50 ma f sk 1?x1? rf b915b 902- 928 mhz 19.2 kba ud 10 ma 2.5-3.4 v 50 ma f sk 1?x1? ordering inform ation pa r t numbe r j unc tion te mp. ra nge (1 ) pack ag e micrf 610 t r ?20 to + 75c 11.5 x 14.1mm micrf 610z t r ?20 to + 75c 11.5 x 14.1mm block di agram vc o bia s rs si data ixo dat a clk ld ant lna sa ll e n -k e y sa ll e n -k e y ma i n fi lter ma i n fi lter if a m p pa div 2 if a m p lo-b u f f e r p a -b uffe r f r eq ue nc y s y nthe sise r dem o d u l a t o r cl o c k r e c o ver y mo du l a to r d e v i a t i o n co nt r o l r ssi xc o contr o l logic cs io scl k micrf 610
mic r el, inc . micrf 610/m i crf 610z july 200 6 4 m999 9-12 020 5 pin c onfi gur ation 10 micrf 610 t r 11.5 x 1 4 .1 m m (top v i e w ) pin d e s c r i ption pin numbe r pin na me ty pe pin f unc tio n 1 n c n o t conn ected 2 n c n o t conn ected 3 cs i chip se lect, three w i re progr a mming interfac e 4 sclk i clock, three w i re progr ammin g interface 5 io i/o data, three w i r e progr ammin g interface 6 dat a ixo i/o data rece ive/transmit, bi-dir e c t ional 7 dat a clk o data clock rec eive/transmit 8 l d o l o c k d e t e c t 9 rssi o receiv e sig nal strength in dicat o r 1 0 g n d g r o u n d 1 1 g n d g r o u n d 1 2 g n d g r o u n d 1 3 a n t i / o r f i n / o u t 1 4 g n d g r o u n d 1 5 v d d v d d (2.0-2.5v ) 1 6 g n d g r o u n d
micrel, inc. MICRF610/MICRF610z july 2006 5 m9999-120205 absolute maximum ratings (1) supply voltage (v dd ) ...................................................+2.7v voltage on any pin (gnd = 0v). ..................... -0.3v to 2.7v lead temperature (solderi ng, 5 sec.) ...................... +225c storage temperature (t s ) ............................-30c to +85c esd rating (3) ..................................................................2kv operating ratings (2) supply voltage (v in ) ..................................+2.0v to +2.5v rf frequenci es................................. 868mhz to 870mhz data rate (nrz) ................................................ <15 kbps ambient temperature (t a ) .......................?20c to +75c electrical characteristics f rf = 868.3mhz, data rate = 15.2kbps, v dd = 2.5v; t a = 25c, bold values indicate ?20c < t a < +75c, unless noted. parameter condition min typ max units power supply 2.0 2.5 v power down current 0.3 a standby current 280 a vco and pll section tunable with on-chip cap bank 16 mhz crystal oscillator frequency tuning range -30 +40 ppm crystal initial tolerance -10 +10 ppm crystal temperature tolerance -10 +10 ppm rx 868.3mhz ? rx 868.95mhz 200 s rx ? tx, same frequency, measured @ frequency offset < 10khz 150 s tx ? rx, same frequency, time to good data 300 s standby ? rx, 2.0 ms switch time standby ? tx 2.0 ms crystal oscillator start-up time xco_tune=13 750 s transmit section r load = 50 ? , pa2..0:111 8.5 dbm output power r load = 50 ? , pa2..0:001 -6 dbm over temperature range 1 db output power tolerance over power supply range 3 db r load = 50 ? , pa2_0: 111 26 ma tx current consumption r load = 50 ? , pa2_0: 001 14 ma tx current consumption variation r load = 50 ? , pa2_0: 111 2.5 ma binary fsk frequency separation (5) limited by receiver bw 20 400 khz data rate nrz 0 15.2 kbps occupied bandwidth 868.95mhz, 15.2kbps, = 12 ( 85khz), -36dbm (rbw=10khz) 450 khz harmonics 868 -30 dbm spurious emission in restricted bands < 1ghz -54 dbm spurious emission < 1 ghz -36 dbm spurious emission > 1 ghz etsi en 300-220 -30 dbm
micrel, inc. MICRF610/MICRF610z july 2006 6 m9999-120205 parameter condition min typ max units receive section all functions on 13.6 ma lna bypass 11.2 ma switch cap filter bypass with lna 11.3 ma rx current consumption bypass of switch cap and lna 8.9 ma rx current consumption variati on over temperature 3 ma 2.4 kbps, = 16, sc=50 khz -111 dbm 4.8 kbps, = 16, sc=50 khz -110 dbm 4.8 kbps, = 4, sc=31 khz -108 dbm 15.2 kbps, =8, sc=200 khz -107 dbm receiver sensitivity, (ber < 10 -3 ) 15.2 kbps, =2, sc=67 khz -105 dbm receiver maximum input power 15.2 kbps, =12 -8 dbm over temperature 3 db receiver sensitivity tolerance over power supply range 1 db receiver bandwidth 50 350 khz co-channel rejection 15.2 kbps, = 8, sc=133 khz -6 db 200 khz spacing 500 khz spacing adjacent channel rejection 1 mhz spacing offset 1mhz 59 db offset 2mhz 62 db offset 5mhz 51 db offset 10mhz 56 db blocking desired signal: 15.2 kbps, =8, 3db above sens, sc=133 khz offset 30mhz 70 db 1db compression -35 db input ip3 2 tones with 1mhz separation -25 dbm input ip2 dbm lo leakage -90 dbm spurious emission < 1ghz -57 dbm spurious emission > 1ghz etsi en 300-220 -47 dbm input impedance 32+j4 ? rssi dynamic range 50 db pin = -110 dbm 0.9 v rssi output range pin = -60 dbm 2.1 v digital inputs/outputs logic input high 0.7v dd v dd v logic input low 0 0.3v dd v clock/data frequency (4) 10 mhz clock/data duty cycle (4) 45 55 % notes : 1. exceeding the absolute maximum rating may damage the device. 2. the device is not guaranteed to function outside its operating rating. 3. devices are esd sensitive. handling precautions re commended. human body model, 1.5k in series with 100pf. 4. guaranteed by design.
micrel, inc. MICRF610/MICRF610z july 2006 7 m9999-120205 programming general the MICRF610 functions are enabled through a number of programming bits. the programming bits are organized as a set of addressable control registers, each register holding 8 bits. there are 23 control registers in total in the MICRF610, and they have addresses ranging from 0 to 22. the user can read all the control register s. the user can write to the first 22 registers (0 to 21); the register 22 is a read-only register. all control registers hold 8 bits and all 8 bits must be written to when accessi ng a control register , or they will be read. some of the registers do not utilize all 8 bits. the value of an unused bit is ?don?t care.? the control register with address 0 is referred to as controlregister0, the control register with address 1 is controlregister1 and so on. a summary of the control registers is given in the t able below. in addition to the unused bits (marked with?-?) there are a number of fixed bits (marked with ?0? or ?1?). always maintain these as shown in the table. the control registers in MICRF610 are accessed through a 3-wire interface; clock, data and chip select. these lines are referred to as sclk, io, and cs, respectively. this 3- wire interface is dedicated to control register access and is referred to as the control inte rface. received data (via rf) and data to transmit (via rf) are handled by the dataixo and dataclk (if enabled) lines; th is is referred to as the data interface. the sclk line is applied exter nally; access to the control registers are carried out at a rate determined by the user. the MICRF610 will igno re transitions on the sclk line if the cs line is inactive. the MICRF610 can be put on a bus, sharing clock and data lines with other devices. all control registers should be written to after a battery reset. during operation, it is sufficient to write to one register only. the MICRF610 will automatically enter power down mode after a battery reset. address data a6?a0 d7 d6 d5 d4 d3 d2 d1 d0 0000000 lna_by pa2 pa1 pa0 sync_en mode1 mode0 ?1? 0000001 ?1? ?0? ?0? ?0? rssi_en ld_en pf_fc1 pf_fc0 0000010 ?0? ?sc_by? ?0? ?pa_by? ?0? ?0? ?0? ?0? 0000011 ?1? ?1? ?0? vco_ib2 vco_ib1 vco_ib0 vco_freq1 vco_freq0 0000100 ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? 0000101 - - ?0? ?1? ?0? ?0? ?0? ?0? 0000110 - ?0? ?0? ?0? bitsync_clks2 bitsync_clks1 bitsync_clks0 bitrate_clks2 0000111 bitrate_clks1 bitrate_clks0 refclk_k5 refcl k_k4 refclk_k3 refclk_k2 refclk_k1 refclk_k0 0001000 ?1? ?1? scclk5 scclk4 scclk3 scclk2 scclk1 scclk0 0001001 ?0? ?0? ?1? xcotune4 xcotune 3 xcotune2 xcotune1 xcotune0 0001010 - - a0_5 a0_4 a0_3 a0_2 a0_1 a0_0 0001011 - - - - n0_11 n0_10 n0_9 n0_8 0001100 n0_7 n0_6 n0_5 n0_4 n0_3 n0_2 n0_1 n0_0 0001101 - - - - m0_11 m0_10 m0_9 m0_8 0001110 m0_7 m0_6 m0_5 m0_4 m0_3 m0_2 m0_1 m0_0 0001111 - - a1_5 a1_4 a1_3 a1_2 a1_1 a1_0 0010000 - - - - n1_11 n1_10 n1_9 n1_8 0010001 n1_7 n1_6 n1_5 n1_4 n1_3 n1_2 n1_1 n1_0 0010010 - - - - m1_11 m1_10 m1_9 m1_8 0010011 m1_7 m1_6 m1_5 m1_4 m1_3 m1_2 m1_1 m1_0 0010100 ?1? ?0? ?1? ?1? ?0? ?1? ?0? ?1? 0010101 - - - - feec_3 fe ec_2 feec_1 feec_0 0010110 fee_7 fee_6 fee_5 fee _4 fee_3 fee_2 fee_1 fee_0 table 1. control registers in MICRF610
mic r el, inc . micrf 610/m i crf 610z july 200 6 8 m999 9-12 020 5 writing to th e con t rol re gisters in mi crf 610 writing: a nu mber of o c te ts are ente r e d into MICRF610, followe d by a loa d -sign a l to a c tivate the ne w setting. makin g the s e events i s ref e rred to as a ?write sequ en ce.? it is po ssi ble to update all, 1 , or n control regi sters in a write seq uen ce. t he a ddress to write to (o r the first a d d r ess to write to ) can be a n y valid add re ss (0 -21). t he io l i ne is alway s an in put to the micrf 610 (out put from u s er) wh en writing. w h at to w r ite: ? the a d d r e ss of the control regi ste r to write to (or if more tha n 1 control re gist er shoul d be written to, the address o f the 1 st control regi ster to write to). ? a bit to enable rea d ing or writing of the control regi sters. thi s bit is call ed the r/w bit. ? the value s to write into the control regi st er(s). fi el d c o m m e n t s address: a 7-bi t field , rangin g fr om 0 to 21 . ms b i s w r itte n fir s t. r/w bi t: a 1-bi t field , = ?0? fo r w r iting values: a number of octe ts (1-22 o c te ts). m sb in ev er y octet is w r itten first. the first octet is w r itten to th e contr ol register w i th the spe c ifie d add ress ( = ?address?) . the n e x t octe t (if th ere i s on e) i s w r itten to the contr ol regi ster w i th add ress = ?ad d re ss + 1? and so on. t a b l e 2. w r itin g to th e con t ro l reg i sters h o w t o wr i t e : bring cs a c tive to start a write sequ en ce. the a c tive state of the cs lin e is ?hi gh.? use the sclk/i o seri al inte rface to clo ck ?add re ss? an d ?r/w? bit a n d ?value s? i n to the micrf 610. micrf 610 will sampl e the io line at negative edge s of sclk. make sure to chan ge the state of the io line before the negative ed ge. refer to fi gure s bel ow. bring cs in active to ma ke an inte rn al load-sig n a l and compl e te the write - sequ en ce. t h e t w o d i fferen t w a y s to ?p ro g ram th e ch ip ? are: ? write to a nu mber of co ntrol regi sters (0-22 ) wh en the regi ste r s have in cre m e n tal add re sse s (write to 1, all or n regi sters) ? write to a n u mbe r of co ntrol registe r s when the regi sters hav e non-i n crem ental add re sses. writing to a single regis t er writing to a control regi ster with address ?a6. a5, ?a0? is descri bed h e re. durin g ope ration, writing to 1 registe r is sufficie n t to chang e the wa y t he transcei v er wo rks. typical example: ch ange fro m re ceive mod e to power-do w n. fi el d c o m m e n t s address: 7 bit = a6, a5 , ?a 0 (a6 = m s b. a0 = l s b) r/w bi t: ?0? for w r iting values: 8 bits = d7 , d6 , ? d 0 (d7 = msb , d0 = lsb) t a b l e 3. ? a d d res s? an d ?r/w b i t? tog e ther ma ke 1 o c t e t. in add itio n, 1 octet w i th pr og ramming bits i s entere d . t o tall y, 2 octets are cloc ked into th e micrf 61 0. h o w t o wr i t e : ? bring cs hig h ? use sclk an d io to clock in the 2 octets ? bring cs lo w c s sclk io a6 a5 a0 rw d7 d6 d2 d1 d0 address of register i rw data to write into register i internal load pulse made here f i g u re 1. ho w to w r ite to a s i n g l e con t ro l reg i ster in figure 1, io is cha nge d at positive edge s of scl k . the micrf 610 sample s the i o line at ne gative ed ge s. the value of the r/w bits i s al ways ?0? fo r writing. w r iting to a l l r e gisters after a p o we r-o n, all writ able regi ste r s m u st be written. this is descri bed he re. writing to all registe r ca n b e done at any time. to get the simple st firm ware, alway s write to all re gisters. the p r ice to pay for the s i mplic i ty is inc r eased write-time, w h ic h lead s to incre a se d time for cha ngin g the way the micrf 610 works. wha t to w r i t e fi el d c o m m e n t s address: ?000000? (addre s s of the fi rst regi ster to w r ite to, w hich i s 0) r/w bi t: ?0? for w r iting v a l u e s : 1 st octe t: w anted v alues for control r egiste r0. 2 nd octet: w anted v alues for controlr egister1 and so on for all of the octe ts. so th e 22 nd octet: w anted v alues for c ontr olregister21 . re fe r to th e spe c ifi c se ction s o f this do cumen t for a c tua l v alues. t a b l e 4. ? a d d res s? an d ?r/w b i t? tog e ther ma ke 1 o c t e t. in total, 23 octets are clo c ked into the micrf 610.
mic r el, inc . micrf 610/m i crf 610z july 200 6 9 m999 9-12 020 5 h o w t o wr i t e : ? bring cs hig h ? use sclk an d io to clock in the 23 octet s ? bring cs lo w refer to the figure i n th e next se cti on, ?writing to n regi sters havi ng incr em ent al addresse s?. writing to n regis t ers ha v i ng incremental addre s ses in addition to enterin g all b y tes, it is also possible to e n ter a set of n bytes, sta r ting from add re ss i = ?a6, a5, ? a0?. typical exam ple: clo ck in a new set of frequ en cy dividers (i.e. chan ge the rf fre que ncy). ?in c rem ental add re sses?. regi sters to be written a r e located in i, i+1, i+2. wha t to w r i t e: fi el d c o m m e n t s address: 7 bit = a6, a5, ?a 0 (a6 = msb. a0 = lsb) (addre s s of fi rst by te to w r ite to) r/w bi t: ?0? for w r iting values: n* 8 bi ts = d 7 , d 6 , ? d 0 ( d 7 = m s b, d 0 = ls b ) ( w r i t t e n t o c o nt r o l r e g . wi t h address ?i?) d 7 , d 6 , ? d 0 ( d 7 = m s b, d 0 = ls b ) ( w r i t t e n t o c o nt r o l r e g . wi t h address ?i+1?) d 7 , d 6 , ? d 0 ( d 7 = m s b, d 0 = ls b ) ( w r i t t e n t o c o nt r o l r e g . wi t h address ?i+n-1?) t a b l e 5. ? a d d res s? an d ?r/w b i t? tog e ther ma ke 1 o c t e t. in addition, n octets with progra mming bi ts are e n tere d. totally. 1 +n octets a r e clo c ked into the micrf 610. h o w t o wr i t e : ? bring cs hig h ? use sclk an d io to clock in the 1 + n octets ? bring cs lo w in figure 1, io is cha nge d at positive edge s of scl k . the micrf 610 sample s the i o line at ne gative ed ge s. the value of the r/w bits i s al ways ?0? fo r writing. c s sclk io a6 a5 a0 rw d7 d6 d2 d1 d0 address of first rw register to write to, register i data to write into register i internal load pulse made here data to write into register i+1 f i g u re 2. ho w to w r ite to man y co n t ro l reg i sters readin g fro m the con t r o l registers in micrf6 1 0 the ?read -se quen ce ? is: 1. enter add re ss and r/w bit 2. cha nge di re ction of io line 3. rea d out a numb e r of octet s an d cha nge io dire ction ba ck agai n. it is po ssi ble to rea d all, 1 or n regi sters. t he add ress to read f r om (or the first a d d r ess to rea d from) can be any valid address (0-2 2). re ad ing is not de structive, i.e. value s are not ch an ged. t he io li ne i s output f r om th e mi crf61 0 (input to u s e r) fo r a part of the rea d -seque nce. refer to pro c ed ure de scription b e lo w. a read -sequ ence is describ ed fo r re ading n re gi sters, whe r e n is n u m ber 1 - 23. readin g n register s fro m micrf61 0 cs sclk io a6 a5 a0 rw d7 d6 d0 address of register i rw data read from reg. i s imple time i o input i o output f i g u re 3. ho w to read fro m man y co n t ro l reg i ster s in figure 3, 1 regi ster i s read. the ad d r ess is a6, a5, ? a0. a6 = msb. the data read out i s d7, d6, ? d 0. the value of the r/w bit is al ways ?1 ? for re ading. sclk and i o togethe r form a se rial interface. sclk is applie d externally for rea d i ng as well a s for writin g. ? bring cs a c tive ? en te r ad dr ess to r e a d fr om (o r th e fir s t add re ss to read from) (7 bits) an d ? the r/ w bit = 1 to enable readin g ? make th e io line an inp u t to the user (set pi n in tris tate) ? rea d n o c tet s . the fi rst rising edg e of sclk will set the io as a n outp u t from the micrf 610. micrf will chang e the io line at po siti ve edg es. the u s e r sh ould read th e io line at the ne gative edge s. ? make the io l i ne an outp u t from the user again.
mic r el, inc . micrf 610/m i crf 610z july 200 6 10 m999 9-12 020 5 progr am ming i n terface timi ng figure 4 and table 6 sho w the timi ng sp ecification for the 3-wi re se rial prog ram m ing interfa c e. c s s clk i o a6 a5 a0 rw d7 d6 d2 d1 d0 address register data register loa d tscl twrite tread thigh tlow tper tcsr traise tfall f i g u re 4. program min g in terface t i min g valu es sy mbol para mete r m i n . t y p . ma x . units t per min. peri od of sclk (volta ge divid e rs on io lines w i ll sl o w do w n th e w r it e/rea d freq uenc y) 5 0 n s t h igh min. hig h time of sclk 20 ns t l o w min. lo w time o f sclk 20 ns tfall max. time of fal l ing edg e of sclk 1 s trise max. time of ris ing e d g e of sclk 1 s t csr max . time of ris ing e d g e of cs to falling e d g e of sclk 0 ns t c sf min. del a y fro m rising e dge of cs to rising edg e of sclk 5 ns t w rite min. del a y fro m valid io to fallin g ed ge of s c lk dur ing a w r it e op eratio n 0 ns t r ead min. del a y fro m rising e dge of sclk to vali d io during a r ead o per ation (assumin g lo ad capacita n ce of io is 25pf ) 7 5 n s t a b l e 6. timing sp ecification fo r th e 3- w i r e pro g rammin g in terface
mic r el, inc . micrf 610/m i crf 610z july 200 6 11 m999 9-12 020 5 po w e r on re set whe n applyin g voltage to the micrf61 0 a power on reset state is ente r ed. duri ng th e time perio d of powe r on reset, the micrf 61 0 sho u ld be consi dered to be in an un kn own state and the use r sh ould wait until com p leted (se e table 6). the po we r on re set timi ng given in ta ble 6 is coveri ng all con d itions and shoul d b e treated a s a maximum de lay time. in some application it might be ben eficial to mini mize the power on reset time. in these ca se s we re co mme nd to follow bel ow pro c ed ure: programming summar y ? use cs, scl k , and io to get acce ss to the control regi sters in m i crf6 10. ? sclk is u s er-co n troll ed. ? write to the micrf 610 at positive edg es (micrf61 0 read s at negat ive edge s). ? rea d from th e micrf 610 at negative e dge s (micrf61 0 write s at posit ive edge s) ? after pow er-on: w r ite to the c o mplete set of control re gist ers. ? address field is 7 bits long. enter msb firs t. ? r/w bit is 1 b i t long (?1 ? for read, ?0 ? for write ) ? addre s s and r/w bit toget her ma ke 1 o c tet ? all control reg i sters are 8 bi ts long. enter/read m s b in every oc tet firs t. ? always write 8 bits to/r ead 8 bits from a control regi ster. thi s is the ca se fo r regi sters wit h less than 8 used p r og rammi ng bits as well. ? writing: brin g cs high, writ e address an d r/w bit followed by the new values to fill into the addresse d co ntrol re giste r (s) an d bri ng cs low for loadin g , i.e., activation of the ne w co ntrol regi ster values. ? rea d ing: brin g cs hi gh, write addre s s a nd r/w bit, set io as an input, rea d present co ntents of the addresse d co ntrol re giste r (s), bri ng cs l o w an d set io an out put.
mic r el, inc . micrf 610/m i crf 610z july 200 6 12 m999 9-12 020 5 f r eq uency s y n t h esiz e r a 6 ?a 0 d 7 d 6 d5 d 4 d3 d2 d1 d 0 000 101 0 - - a 0 _ 5 a 0 _ 4 a 0 _ 3 a 0 _ 2 a 0 _ 1 a 0 _ 0 000 101 1 - - - - n 0 _ 1 1 n 0 _ 1 0 n 0 _ 9 n 0 _ 8 000 110 0 n 0 _ 7 n 0 _ 6 n 0 _ 5 n 0 _ 4 n 0 _ 3 n 0 _ 2 n 0 _ 1 n 0 _ 0 000 110 1 - - - - m 0_11 m 0_10 m 0 _ 9 m 0 _ 8 000 111 0 m 0 _ 7 m 0 _ 6 m 0 _ 5 m 0 _ 4 m 0 _ 3 m 0 _ 2 m 0 _ 1 m 0 _ 0 000 111 1 - - a 1 _ 5 a 1 _ 4 a 1 _ 3 a 1 _ 2 a 1 _ 1 a 1 _ 0 001 000 0 - - - - n 1 _ 1 1 n 1 _ 1 0 n 1 _ 9 n 1 _ 8 001 000 1 n 1 _ 7 n 1 _ 6 n 1 _ 5 n 1 _ 4 n 1 _ 3 n 1 _ 2 n 1 _ 1 n 1 _ 0 001 001 0 - - - - m 1_11 m 1_10 m 1 _ 9 m 1 _ 8 001 001 1 m 1 _ 7 m 1 _ 6 m 1 _ 5 m 1 _ 4 m 1 _ 3 m 1 _ 2 m 1 _ 1 m 1 _ 0 the frequ en cy synthe sizer co nsi s ts of a voltage -co n trolled oscillator (v co), a cry s tal oscill ator, ph ase select pre s cale r, progra mmabl e freque ncy dividers a nd a p hase- detecto r. the length of th e n, m, and a regi sters a r e 12, 12 and 6 re spe c tively. the n, m, an d a values can be cal c ulate d fro m the formula : () ( ) a n 16 f 2 a n 16 f m f f rf vco xco phd + = + = = , m 0 1 a < n f phd : phase d e tector com p arison fre que ncy f xco : crystal oscillator frequency f vco : voltage controlled oscillator frequency f rf : input/output rf freq ue ncy there a r e t w o sets of ea ch of the divide fa ctors (i.e. a0 and a1 ). storing the ?0? a n d the ? 1 ? fre q uen cy in the 0- a nd the 1 re giste r s re spe c tively, does the 2 - fsk. the re ceive freque ncy mu st be sto r ed i n the ?0? regi sters. c r y s tal oscillator (x c o ) a d r d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 1 0 0 1 ? 0 ? ? 0 ? ? 1 ? x c ot une4 x c ot une3 x c ot une2 x c ot une1 x c ot u n e 0 the cry s tal oscillator i s a reference for the rf output freque ncy an d the lo freque ncy i n t he re ceiver. it is possibl e to tune the internal cr y s tal oscillator by switching in intern al capa citan c e u s ing 5 tune bits xcotu ne4 ? xcotun0. the benefit of t uning the crystal oscillator is to eliminate the initial tolerance an d the tole ran c e ove r temperature and agi ng. by usi ng the crystal tuning f eature the noi se ba n d width of the receiver ca n be re du ced a nd a highe r se nsi t ivity is ach i eved. when xcotun e 4 ? xcotune 0 = 0 no internal cap a cito rs a r e conn ecte d t o the cry s tal pi ns. whe n x c otu ne4 ? x c otu ne0 = 1 all o f the internal cap a citors are con n e c ted t o the crysta l pin s . figure 5 sh o w s the tuni ng range. - 45. 0 - 35. 0 - 25. 0 - 15. 0 -5 . 0 5. 0 15. 0 25. 0 35. 0 45. 0 55. 0 0 4 8 1 21 62 02 42 83 2 [ x co _t u n e val u e ] [ ppm ] figur e 5 . xco tun in g the typical start up time for the crystal oscillator (default xco_tun e =1 3) i s ~7 50u s. if more ca pacita n ce i s adde d (higher xco_tune val ue), then the st art-up time will be longe r. to save current in the crysta l oscillator start-up period, the xco is tu rne d on befo r e a n y other ci rcu i t block. whe n the xco ha s set t led, re st of t he circuit will be tu rn ed o n . no prog ram m ing shoul d be m ade du ring thi s peri od. the current con s um ption durin g the pre s tart p e ri od is approximatel y 280 a. vco a 6 .. a 0 d7 d 6 d 5 d4 d3 d2 d1 d0 000 001 1 ? 1 ? ? 1 ? ? 0 ? vc o_ib 2 vc o_ib 1 vc o_ib 0 v c o _ f r e q 1 vc o_ f r eq 0 the vco ha s no external compo nent s. it has three bit to set the bi as current an d two bit to set th e vco frequ ency. these five bits are set by t he rf fre que ncy, as follo ws: r f freq . vc o_ib 2 vc o_ib 1 vc o _ i b 0 v c o _ f r e q 1 v co_freq0 8 6 8 m h z 0 1 1 0 1 ta ble 7 . vco bit se tting the bias bit will optimi z e the phase noise, and the frequency bit will cont rol a capa citor bank in the vco. the tuning ran ge the rf freq u ency ve rsus varacto r volta ge i s depe ndent o n the vco freque ncy se tting, and ca n be s h ow n in f i gu r e 6 .
mic r el, inc . micrf 610/m i crf 610z july 200 6 13 m999 9-12 020 5 tuning range 800 850 900 950 1000 00 , 5 11 , 5 22 , 5 varactor v o ltage (v) frequency (mhz) '10' '11' f i g u re 6. rf freq u e n c y v s . vara cto r vo ltag e a nd vco fr e que nc y bit (v = 2.25v) dd lock dete ct a 6 .. a 0 d7 d6 d 5 d 4 d3 d2 d1 d0 000 000 1 ? 1 ? ? 0 ? ? 0 ? ? 0 ? r ssi_e n ld _en pf_fc 1 pf_fc 0 a lock dete c t o r ca n be en a b led by settin g ld_ en = 1. whe n pin l d is high, it indi cate s that the pll is in lock. whe n enteri n g tx, the proce dure is first to load the tx word an d the n turn o n the pa stage. during th e pa ram p up time, the ld sign al ma y indicate ou t of lock. it is first when the p a stage i s f u lly on that the ld signal will indicate in ?lock?. durin g tra n smi s sio n , the l o ck dete ct signal will have transitions and the user should therefore, ignore the lo ck d e tect si gn al. modes of operation a 6 .. a 0 d7 d6 d 5 d 4 d3 d2 d1 d0 000 000 0 l n a_by p a 2 p a 1 p a 0 sy nc_en m ode1 m ode0 ? 1 ? m o d e 1 m o d e 0 s t a t e c o m m e n t s 0 0 pow e r dow n keeps regi ster con f iguration 0 1 standby only cry s tal o s cilla tor runni ng 1 0 receiv e f u l l re ceiv e 1 1 transmit full tra n smi t ex pa sta t e
mic r el, inc . micrf 610/m i crf 610z july 200 6 14 m999 9-12 020 5 transc eiv e r sy nc/non-s y nchronous mode a 6 .. a 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 000 00 0 0 l n a _ b y p a 2 p a 1 p a 0 s y nc _e n mode 1 mode 0 ? 1 ? 000 01 1 0 - ? 0 ? ? 0 ? ? 0 ? bits ync_clks 2 b its y nc_clks 1 bits ync_clks 0 b itrate_c lks2 000 01 1 1 bitrate_c lks1 bitrate_c lks0 refclk_ k 5 refclk_ k 4 r efclk_ k 3 r e f c l k _ k 2 r e f c l k _ k 1 refclk_ k 0 s y n c _ e n s t a t e c o m m e n t s 0 r x : b i t sy nchroniza t ion o f f transparen t re cepti on o f da ta 0 t x : datacl k pi n o f f transparen t tra n sm ission o f data 1 r x : b i t sy nchroniza t ion on bit- clo c k i s gen erated by tran sce iv er 1 t x : datacl k pi n on bit- clo c k i s gen erated by tran sce iv er whe n sync_ en = 1, it wil l enable the bit synch r o n i z er i n receive mo d e . the bit synchroni ze r clo ck nee ds to be prog ram m ed, see cha p ter bit synchroni ze r. the synchronized clock will be set out on pit dataclk. in tran smit m ode, when s y nc_e n = 1, the cl ock sign al on pin data clk is a p r og ra mmed bit ra te clo c k. no w the transceive r control s the a c t ual data rat e . the data to be transmitted will be sampled on ri sing edge of datacl k. the micro co ntrol l er can the r e f ore u s e the negative ed ge to cha nge th e d a ta to be tra n s mitted. the clo ck used fo r this purp o se, bitrate-clo c k, i s p r o g ra mme d in the sam e way as the mod u l a tor clo c k an d the bit synchroni ze r cl ock: lks) -bitrate_c (7 xco k bitrate_cl 2 refclk_k f f = whe r e f bit r at e_clk : t he clo c k freq uen cy use d to cont rol th e bit rate, shoul d be e qual to the bit rate (bit rate of 2 0 kbit/se c requi res a clo c k freque ncy of 2 0 khz) f xco : crystal oscillator frequency refcl k _k: 6 b i t divider, values bet wee n 1 and 63 bitrate_cl k s: bit rate setti ng, value s be tween 0 an d 6 data inter f ac e the micrf6 10 interfa c e can be divided in to two sep a rat e interfaces, a ?p rog r am ming inte rfa c e? and a ?data interface?. th e ?pro grammi ng inte rfa c e? ha s a th ree wi re seri al p r o g ra mmable interface and is d e scrib ed i n chapte r programmin g . the ?data in terface ? can be prog ram m ed to syn c -/non - synchro nou s mode. in sy n c hrono us m o de the MICRF610 is defined a s ?ma s ter? a nd provid es a data clo c k that allows users to utilize low co st mi cro controller reference freque ncy. the data i n terface is defi ned in su ch a way that al l use r actions shoul d take pl ace on falling edge and i s illust rated figure 7 and 8. the two figures illustrate the relationshi p betwe en da taclk a nd dataixo in re ceive m o de an d transmit mode. micrf 610 will present dat a on ri sing edge and the ?user? sam p le data on fa lling edge in receive mo de. dataixo dataclk f i g u re 7. data in terface in recei v e mo d e t he user pr es ents d a ta on falli ng e dge a n d micrf 6 10 s a mpl e s on risi ng ed ge i n transmit mod e . dataixo dataclk f i g u re 8. data in terface in tran smit mo d e recei ver the re ceive r is a ze ro inte rmedi ate freq uen cy (if) type in orde r to make cha nnel filtering p o ssibl e with low-p o we r integrated low-pass filters. t he receive r con s ist s of a low noise am plifier (l na) th at drive s a qu a d ratu re mixe r pair. the mixer o u tputs feed t w o ide n tical sign al ch ann els i n pha se qu adrature. each cha nnel in clu des a pre - a m plifier, a third o r d e r sallen-key rc l o wpa s s filter from stron g adja c ent cha nnel si gnal s and finally a limiter. the main cha nnel filter is a switch e d -c apa cito r i m pleme n tatio n of a six-pol e elli ptic lowpass fil t er . the elliptic filter mi ni mizes the total ca p a citan c e req u ired fo r a gi ven sel e ctivity and dynamic ran ge. the cut - off frequen cy of the sallen-key rc filter can be pro g ra mm ed to four different fre que n c ie s: 100 khz, 150 khz, 230 khz and 340 khz. the demod ulator demod ulate s the i and q c hann el output s and produ ces a digital data o u tput. if detects the relative phase of the i and q chan nel signal. if the i cha nnel sign al lag s t he q cha nnel, th e fsk tone freque ncy li e s a bove th e lo freque ncy (d ata ?1? ) . if the i chan nel l e ads the q ch annel, the fsk tone lies belo w th e lo freq uen cy (data ?0? ) . the output of the re ceiver i s a v a ilable o n the dataixo pin. a rssi circuit (re ceive sig n a l stre ngth i ndicator) indi cate s the received sign al level.
mic r el, inc . micrf 610/m i crf 610z july 200 6 15 m999 9-12 020 5 front end a 6 .. a 0 d7 d6 d 5 d 4 d3 d2 d1 d0 000 000 0 ln a_by p a 2 p a 1 p a 0 sy n c _ e n m o d e 1 m ode0 ? 1 ? a low noi se amplifier in rf re ceivers i s used to boo st the incomi ng sig nal p r io r to th e freq uen cy conversion p r o c e ss. this is im po rtant in ord e r to prevent mixer noise from dominatin g t he ove r all front-e n d noise pe rforman c e. the lna is a two-sta ge am pl ifier and ha s a nominal g a in of approximatel y 23db at 868mhz . the front end ha s a gain of about 33 d b to 35db. the gain va rie s by 1-1. 5db over a 2.0v to 2.5v variation in p o we r su pply. the lna ca n be bypa ssed by setting bit lna_by to ?1?. this ca n b e useful for ve ry stron g in pu t sign al level s . the front-e nd gai n with the l n a bypa sse d is ab out 9 - 10db. the mixers h a ve a gain of about 10db at 868mhz. the input imped a n ce i s sh own in figure 9. figur e 9 . inp u t impe da nc e sallen-ke y f ilters a 6 .. a 0 d7 d 6 d 5 d4 d3 d2 d1 d0 000 000 1 ? 1 ? ? 0 ? ? 0 ? ? 0 ? r ssi_e n ld _en pf_fc 1 pf_fc 0 each ch ann el incl ude s a pre- a m plifier a nd a prefilter, whi c h is a th ree-p o le salle n-ke y lowpa s s filter. it protects the followi ng swit che d -cap acitor filte r from strong ad jace nt cha nnel sign als, an d it also wo rks a s a n anti-ali a si n g filter. the pre a mpli fier has a g a in of 22.23 db. the maximum output voltag e swin g i s a bout 1.4vp p for a 2.25v powe r sup p ly. in ad dition, the if amplifier al so perfo rm s o ffset can c ell a tion. gain varie s b y less than 0 . 5db over a 2.0 ? 2.5v variatio n in powe r supply. the third order salle n-key lowp ass filte r is p r og ram m able to fo ur diffe rent cut-off freque nci e s a c cordi ng to the table belo w : pf_fc1 pf_fc0 cut-off fr eq. (khz) 0 0 1 0 0 0 1 1 5 0 1 0 2 3 0 1 1 3 4 0 s w i t ched ca pacitor filte r a 6 .. a 0 d7 d6 d5 d 4 d3 d 2 d1 d 0 000 100 0 ? 1 ? ? 1 ? scc l k 5 s c c l k 4 scc l k 3 s c c l k 2 scc l k 1 s c c l k 0 the m a in ch ann el filter is a switch ed-capa citor implementation of a six-pole e lliptic l o w pass filter. the elliptic filter minimized the to tal capaci tance required for a given sele ctivity and dyn a m ic ra n ge. t he cut-off fre quen cy of the switch ed-cap a cito r filter is adju s table by cha nging the clo ck freq uen cy. the cl ock fre quen cy is d e s ign ed to be 20 times the cut-off freque ncy. t he clo c k freque ncy is derived fro m the reference crystal os cillator. a programmable 6-bit divider divides the frequency of the cr ystal oscillator. the cut-off freque ncy of the filter is given by: scclk 40 f f xco cut ? = f cut : filter cutoff frequen cy f xco : crystal oscillator frequency scclk: swit ched capa citor filt er clock, bi ts sccl k5 -0 1 st ord e r rc l o wp ass filters are con n e c ted to the o u tput of the sc filter to filter the clo ck freque ncy. the lowest cutoff freque ncy in the pre- an d the main cha nnel filter must be set so that the received sign al is passe d with no attenuatio n, which i s freque ncy devi a tion plus mod u lation. if there are any fre que ncy offset bet wee n the tran smitt e r a nd th e receive r , this must also be take n into con s ide r ation. a formula for the receive r ban d w idth can b e sum m a rized a s follows: 2 / baudrate f f f dev offset bw + + + = whe r e f bw : nee ded receiver ban dwidth, f c ut above sho u ld not be small e r than f bw (hz) f offset : total freque ncy offset between receive r a n d transmitter (hz ) f dev : single-si ded freq uen cy deviation baudrate: the baud rate gi ven is bit/se c in battery op erated appli c ations th at do not nee d very high selectivity, th e main channel filter ca n be bypasse d by sc_by=1. this will reduce t he rx current consumption w i th ~ 2 ma. rssi a 6 .. a 0 d7 d 6 d 5 d4 d3 d2 d1 d0 000 000 1 ? 1 ? ? 0 ? ? 0 ? ? 0 ? r ssi_e n ld _en pf_fc 1 pf_fc 0
mic r el, inc . micrf 610/m i crf 610z july 200 6 16 m999 9-12 020 5 the fee ca n ope rate in three diffe ren t modes; cou n ting only up-pul se s, only dn-p ulses or cou n ting up+dn pulses. t he n o . of re ceived sym bol s to b e co unted is eithe r 8, 16, 32 or 64. this is set by the feec_0? fe ec_3 c ontrol bit, as follow s : r ssi 3 3 k ohm , 1 nf, 1 5 k bps , b w = 2 0 0 k h z , v d d= 2 . 5 v 0, 5 0, 75 1 1, 25 1, 5 1, 75 2 2, 25 - 120 - 110 - 100 - 9 0 - 80 - 7 0 - 60 - 5 0 i n put pow er [ d b m ] r s si vol t a g e [ v ] f e e c _ 1 f e e c _ 0 fee m o d e 0 0 o f f 0 1 cou n ting u p p u l s e s 1 0 cou n ting d n p ulses 1 1 cou n ting up a nd dn p u lses. up increme nts the counter, dn decrem ents it. f eec_3 f eec_2 no . o f sy mb o l s u sed fo r th e mea s u rem en t 0 0 8 0 1 1 6 1 0 3 2 1 1 6 5 f i g u re 10. rssi vo ltag e a typical plot of the rssi voltage a s function of input power i s sh o w n in fig u re 10. the rs si has a dy namic rang e of ab o u t 50db fro m about -110 db m to -60 d bm input power. the rssi can be use d as a sig nal pre s en ce i n d i cator. whe n a rf signal is re cei v ed, the rssi output incre a se s. this could be used to wake up ci rcuitry that is n o rm ally in a slee p mode configu r ation to conserve battery life. ta ble 8 . feec contr o l bi t the re sult of the mea s u r e m ent is the f ee value, thi s can be read fro m re giste r wi th add re ss 0010 110b. negative values are stored a s a bi nary n o b e tween 000 0000 an d 1111 111. t o cal c ulate the negati v e value, a two?s compl e me nt of this value must be pe rformed. only fee mode s where dn-pul se s a r e c ounte d (1 0 and 1 1 ) will give a negative va lue. another a ppli c ation for whi c h t he rssi coul d be use d is to determi ne if tran smit po we r can b e re du ced in a syst em. if the rssi detects a strong sig nal, it could tell the transmitter to re du ce th e transmit po we r to redu ce cu rre nt con s um ption. fee a6 ..a0 d7 d 6 d5 d 4 d3 d2 d1 d0 001 010 1 - - - - feec _ 3 feec _ 2 feec _ 1 feec _0 001 011 0 f e e _ 7 f e e _ 6 f e e _ 5 f e e _ 4 f e e _ 3 f e e _ 2 f e e _ 1 f e e _ 0 whe n the fee value has been read, th e freque ncy offset can b e cal c ul ated as follo ws: mode up: foffset = r/(2 p)x(fee- ? fp ) the frequ en cy erro r esti mator (fee ) use s inform ation from the de modulato r to cal c ul ate th e fre quen cy offset betwe en th e re ceive f r eque ncy an d the t r an smitter freque ncy. t he outp u t of the fee can be u s ed to tu ne the xco freq ue ncy, both for produ ction calib ration a nd for comp en satio n for cry s tal tempe r ature d r ift and aging. mode dn: foffset = r/(2 p)x(fee+ ? fp ) mode up +dn: foffset = r/(4 p)x(fee) whe r e fee i s the value stored i n the fee regi ster, (fp is the si ngle si ded frequ en cy deviatio n , p is th e n o . of symbol s/data bit counte d and r i s the symbol/data rate. a positive f o ffset me an s that the rece ived sig nal has a highe r freq u ency than the re ceiver freque ncy. to comp en sat e f o r t h is, t he r e ceiv e r s x c o f r equ en cy sho u ld be increa se d. the in put to the fee circuit are the u p an d d o wn pulses from the d e m odulato r . every time a ?1? i s up dated, a n up- pulse is comi ng out of the demod ulato r and the sam e with the dn-pul se every time the ?0? is upd ated. the expecte d no. of pulse s for every receiv e d sym bol is 2 times the modulatio n in dex ( ? ). it is re comm ende d to u s e mode up+dn for t w o rea s on s, you do not n eed to kno w the a c tual freque ncy devi a tion and this mo d e gives the b e st accu ra cy. bit sy nchronizer a 6 .. a 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 000 01 1 0 - ? 0 ? ? 0 ? ? 0 ? bits ync_clks 2 b its y nc_clks 1 bits ync_clks 0 b itrate_c lks2 000 01 1 1 b i t r a t e _ c lks1 bitrate_c lks0 refclk_ k 5 r efclk_ k4 refclk_ k 3 refclk_ k 2 refclk_ k 1 refclk_ k 0
mic r el, inc . micrf 610/m i crf 610z july 200 6 17 m999 9-12 020 5 a bit syn c h r onizer ca n b e en able d in re ceive mo de by sele cting th e synchro n ous m ode (sync_ en =1). the dataclk pin will output a clock with twi c e the frequency of the bit rate (a bit rate of 20 kbit/sec give s a data cl k of 20 khz). a recei v ed symbol/bit on dataix o will be out put on risin g edge of data clk. the micro controll er sho u ld therefo r e sa mple the sym bol/b it on falling edg e of datacl k. the bit syn c hroni ze r uses a clo c k that need s to be prog ram m ed according to the bit rate. t he cl ock freq uen cy sho u ld be 1 6 times the actual bit rate (a bit rate of 20 kbit/se c need s a bit syn c h r oni ze r cl ock with frequ en cy of 320 khz). t he cl ock fre quen cy is set by the fol l owin g formula: lks) -bitsync_c (7 xco k bitsync_cl 2 refclk_k f f = whe r e f bit sync_c l k : the bit syn c h r onizer clo c k freque ncy (16 time s hig her than the bit rate) f xco : crystal oscillator frequency refcl k _k: 6 b i t divider, values bet wee n 1 and 63 bitsync _ c l k s : bit s y nc hronizer s e tting, values betwe en 0 an d 7 refcl k _k i s also u s e d to derive the modulato r cl ock an d the bit rate cl ock. at the begin n ing of a re ce ived d a ta packa ge, the bit synchro n izer clo ck frequ en cy is not synchroni ze d to th e bit rate. when th ese t w o a r e maximum off s et to ea ch ot her, it take s 22 bit/symbols befo r e sync hro n ization is a c hie v ed. tra n smitt e r po w e r ampli f ier a 6 .. a 0 d7 d6 d 5 d 4 d3 d2 d1 d0 000 000 0 l n a_by p a 2 p a 1 p a 0 sy n c _ e n m ode1 m o d e 0 ? 1 ? 000 000 1 ? 1 ? ? 0 ? ? 0 ? ? 0 ? r ssi_e n ld _ e n pf_fc 1 pf_fc 0 the m a ximu m output po wer i s a pproximately 10db m for a 50 ? l oad. t he o u tput p o w er i s p r og rammabl e in seven step s, with approxim ately 3db betwee n each step. bits pa2 ? pa0, control thi s . p a 2 ? pa0 = 1 give the max i mum output po wer. the p o wer a m plifier can be turned off by setting pa2 ? pa0 = 0. for all othe r combi nation s the pa is on and ha s max i mum power when pa2 ? pa0 = 1. the pa will be bypassed if pa_by=1. output power will drop ~14db. it is still possi ble to control the power by pa2 ? pa0. freque nc y modulation fsk modulation is appli e d by switchin g between two sets of dividers (m,n,a). the formula fo r calcul ating the m, n and a value s is given in cha p ter f r eq uen cy synthe sizer. the divider values sto r e d in the m 0 -, n0-, an d a0- regi sters will be used when tran smitting a ?0? and the m1-, n1-, and a1-regi sters will be used to transmit a ?1?. the differen c e betwe en th e two ca rrie r freque ncie s corre s p ond s to the dou ble side d fre que ncy deviatio n . the data to be tra n smitted shall be applie d to pin dataixo (se e cha p ter tra n s ceiver syn c -/ non-synchro nou s mo de o n ho w to use the pi n data cl k). th e dataixo pi n is set a s i n put in transmit mod e and outp u t in receive mo de. usi ng the xco-t u ne bits the mo dule has a b u ilt-in me ch ani sm for tunin g the frequency of the crystal oscilla tor and is often used in combi nation with the f r e quen cy error estimator (fee). the xco tun i ng is de sign ed to elimin a t e or redu ce initial freque ncy tol e ran c e of th e crystal a n d /or the freq uen cy stability over temperature. a proce d u r e for using the xco tuning feature in combi nation with the fee is given belo w . the MICRF610 measures th e freq uen cy offset betwee n the receive r s lo freque ncy a nd the freq uen cy of th e tran smitter. the receiver xco freque ncy can be tun ed until the receive r and tran smitt e r freq uen cie s are e qual. a procedu re like this ca n be calle d during p r od uction (sto ring th e calib rated xco_tun e v a lue), at re gular intervals o r i m pleme n ted in the comm unication pro t ocol whe n the frequ en cy h a s cha nged. the micrf61 0 developm ent system can t e s t this feature. example: in fee, count u p +d own pul ses, co unting 8 bits: a perf e ct c a s e == > fe e = 0 if fee > 0: lo is to o lo w, increa se lo by de cre a sin g xc o_tune value v.v. for fee < 0 fee field ho lds a num be r in th e rang e -1 28, ? , 127. ho wever, it keep s cou n tin g ab ove/belo w the range, whi c h is: if fee = -128 and still counting dwn-pul ses: 1) => -12 9 = +12 7 2) 126 3) 125 to avoid this situation, alwa y s ma ke sur e max co unt is betwe en limits.
mic r el, inc . micrf 610/m i crf 610z july 200 6 18 m999 9-12 020 5 application circuit illustration f i g u re 11. circu it illu stration o f micrf 610, l d o an d mcu figure 11 sh ows a typical se t-up with the micrf 6 10, a low-dro p-o u t voltage re gulator (ldo) and a mikro- controlle r (m cu). when t he micrf 6 1 0 an d the m c u ru ns on the same power sup p l y (min 2.0, max. 2.5v), the io can be co nne cted dire ctly to the m c u. if the m cu ne eds a highe r vdd t han the max. spe c ified vdd of the micrf61 0 (2.5v), voltag e dividers n e ed to be add ed on th e io lines not to overrid e the max. input voltage. figure 12 sh ows a re com m ende d volta ge divide r ci rcuit for a mcu run n i ng at 3.0v an d the micrf 610 at 2.5v. 3k3 18k 3k3 18k 3k3 18k 15k micrf6xx mcu cs sclk io dataixo dataclk ld rssi cs sclk io dataixo dataclk ld rssi f i g u re 12. how to con n ect micrf 610 (2. 5 v) an d mcu (3.0v) assembli ng t h e mi crf610 recomme nd ed re flo w t e mpera t ure profile whe n the micrf 610 module is being autom atically assembl ed to a pcb, care must be ta ken n o t to expose the mod u le fo r temp eratu r e above th e m a ximum spe c ified. figure 13 shows the re comm end ed reflow tempe r ature profile. f i g u re 13. reco mmen d e d reflo w t e mp eratu re r e flo w shock/vibration during reflo w the mod u le has several compo nent s inside which are assembl ed i n a reflo w p r o c e ss. the s e comp one nts may reflow again whe n the mo dule is asse mbled o n to a pcb. it is therefore i m porta nt that t he modul e i s not subj ect ed to any mech ani cal sho ck o r vibration d u rin g this pro c e s s. hand ass embling the micrf 610 it is recomm ende d to use solde r pa ste also d u rin g hand assembli ng o f the mod u le. beca use of t he mo dule ground pad on the bottom side, the m odul e will be assembled most effici ent if the heat i s being su bje c ted to the b o tto m side of the p c b. the heat will be transfer red trough the pcb due the grou nd via s unde r the m odule (see l a yout con s id eratio ns). in ad dition, it is reco mmend ed to use a sold er tip on the signal a n d powe r pad s, to make sure the sold er poi nts are p r op erly melted.
mic r el, inc . micrf 610/m i crf 610z july 200 6 19 m999 9-12 020 5 lay out la y out cons ideration s except for the antenna in put/out put sig nal, only digital and low freque ncy signal s n e ed to inte rface with th e m odule. there is the r efore n o nee d of years of rf expe rtise to do a su ccessful la yout, as lon g as the follo wing fe w p o i n ts a r e being follo we d: recomme nd ed land pattern figure 14 shows a re commen ded l and patte rn that facilitates both automatic and hand assembling. ? prope r g r o u n d is ne eded. if the pcb i s 2-laye r, the bottom layer sho u ld be ke pt only for ground. avoid sign al tra c e s that split the grou nd pla n e . for a 4- layer pcb, it is re com m en ded to keep t he se co nd layer only for grou nd. ? a grou nd via sho u ld be placed clo s e to all the grou nd pin s . the bottom groun d pad shoul d be penetrated wi th 4-16 g r ou n d vias. ? the anten na has a n impe dan ce of ~50 ohm. the antenn a tra c e sho u ld b e kept to 50 oh m to avoid sign al reflect i on a nd l o ss of pe rforma nce. a n y transmissio n l i ne calculator can be used to find the need ed tra c e width given a boa rd buil d up. ex: a trace width of 44 mil (1.12 mm ) gives 50 impeda nce o n a f r 4 b o a r d (diele ctri c con s =4.4) wit h cop per t h ic kne s s of 3 5 m and heig h t (laye r 1 - layer 2 sp aci ng) of 0.61 m m . figur e 1 4 . re c o mme nde d la nd pa tte r n (t op view) ? rf ci rcuitry is se nsitive to voltage supply and therefo r e cau t ion sho u ld b e taken whe n cho o si ng power ci rcuitry. to achieve the best perf o rma n ce, low noi se ldo? s with high pssr should be c h os en . wh at is pr es e n t on th e vo ltag e s u pp ly w ill be dire ctly modulate d to the rf spe c trum cau s in g degradatio n and regul atory issu es. t o make sure you have the right sel e cti on, plea se contact lo cal s a les for the lates t micr el offering s in p o wer manag eme n t and guid a n c e. to avoi d ?picku p? from othe r circuitry on the vdd lines, it is recomme nde d to ro ute the vdd in a sta r config uratio n with de cou p li ng at ea ch ci rcuit r y and at the com m on con n e c tion poi nt (see ab ove layout). if there a r e noi sy ci rcuitry in th e de sign, it is stro ngly re comm end ed to use a sepa rate po we r sup p ly and/o r pla c e lo w va lue resi stors (10o hm s), indu ctors in serie s with the power su ppl y line into these circuitry. ? digital high sp eed lo gic or noi sy circuitry sho u ld/mu s t be at a safe di stan ce from rf circuitry or rf vdd as this might/will cause degradatio n of se nsitivity and cre a te sp uri o u s emission s. example of su ch circui try is l c d displ a y, ch arge p u mp s, rs232, clo c k / data bu s etc.
mic r el, inc . micrf 610/m i crf 610z july 200 6 20 m999 9-12 020 5 package dimensi o ns f i g u re 15. packag e dimen s i o n s ta pe dim e nsions figur e 1 6 . ta p e dime ns ions micrel, inc. 2180 fortune drive san jose, ca 9513 1 usa t e l + 1 (408) 9 44-0 800 f a x + 1 (408) 47 4-1 000 w eb http:/ w w w . m i crel.co m the information f u rnished b y micrel in this data sh eet is belie ved to be accurate and reliable. ho w e ver, no responsibility is a ssumed by micr el for its use. micrel reserves the right to change circuitry a nd specifications at an y time w i tho u t notification to the customer. micrel products are not designed or autho ri zed for use as components in life support app liances, devices or sy stems where malfu nction of a product r e a s o n a b l y b e expected to res u lt in personal injury . life suppo rt devices or sy ste m s are devices or s y stems that (a ) are in tende d f o r s u r g i c a l i m p l a into the bod y or (b) support o r sustain life, and w h o s e failure to perf o rm can be re asonabl y e x pected to result in a significan t injury to th e user. a purchaser?s use or sale of micrel produc ts for use in life support app liances, devices or s y stems is a purchaser?s ow n risk and purchaser agre e s to full y indemnif y micrel for an y damages resulting from such use or sale. c a n n t ? 2005 micrel, in corporated.

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